The present disclosure relates to a method of manufacturing a semiconductor structure, and particularly to a method of manufacturing a semiconductor structure including high density field effect transistors, and a method of generating a design layout for implementing the same.
Printing a lithographic pattern having pitches below lithographic limits of traditional lithographic techniques, e.g., below 80 nm, does not yield patterns with high fidelity. To overcome this problem, design layouts employ periodic patterns including dummy structures and cut masks that remove the dummy structures while preserving device structures. However, continued scaling of semiconductor devices have made it difficult to consistently remove dummy structures without unintended residue structures while protecting device structures. Particularly, making precise cuts to gate structures straddling semiconductor active regions has become very challenging due to the small dimensions in high density semiconductor circuits.